The present invention relates generally to microelectronic devices, and specifically to embedded silicon-germanium source/drains.
As transistor structures continue to become smaller in size, it may be advantageous to employ techniques that increase carrier mobility in the channel region of a transistor by generating strain in the channel and therefore increase device performance. In the case of field effect transistors (FETs), one such technique may be to embed material with a different lattice structure than the channel between the source/drain regions of the FETs, as depicted in FIG. 1. This causes the channel region to stretch or compress to match the atomic lattice of the source/drain regions. For p-type FETs (pFETs, i.e., FETs with p-type channels), this may be accomplished by using embedded silicon-germanium alloy source/drain regions and for n-type FETs (nFETs, i.e., FETs with n-type channels), this may be accomplished by using embedded silicon-carbon source/drain regions.
FIG. 1 depicts a known embodiment of a FET 10 fabricated on a semiconductor substrate 11. The substrate 11 may include isolation regions 12, and a gate 13 having spacers 14 on sidewalls of the gate 13. The location of the gate 13 defines a channel region 17 in the substrate 11. In order to apply stress to the channel region 17, embedded source/drain regions 15 made of a silicon-germanium alloy (for pFETs) or a silicon-carbon alloy (for nFETs) may be formed laterally adjacent to the channel region 17.
In some cases, particularly for deeper source/drain regions 15, “punchthrough” may occur. Punchthrough is when a path exists for parasitic current between the source and the drain other than the intended path through the channel 17. In the pFET 10, this path for punchthrough may occur in region 18. One method of preventing punchthrough is halo implantation, which involves sophisticated angled doping techniques to introduce dopants into the region 18 of the opposite type as in the source/drain regions 15. Because of the complicated nature of halo implantation, a method of fabricating embedded silicon-germanium source/drain regions capable of providing stress to the channel of a FET while reducing the effects of punchthrough without employing halo implantation is desirable.